ti: k3: common: Set L2 latency on A72 cores

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew F. Davis <[email protected]>
Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a

diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index 1ab1af54c549d36d6b125fd39405f4ed0d1666ff..3afca591ec974b80b9af0a071838cb44de53fb70 100644 (file)
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -6,6 +6,8 @@
 
 #include <arch.h>
 #include <asm_macros.S>
+#include <cortex_a72.h>
+#include <cpu_macros.S>
 #include <platform_def.h>
 
 #define K3_BOOT_REASON_COLD_RESET 0x1
@@ -89,6 +91,26 @@ out:
        ret
 endfunc plat_my_core_pos
 
+       /* --------------------------------------------------------------------
+        * This handler does the following:
+        * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
+        * --------------------------------------------------------------------
+        */
+       .globl plat_reset_handler
+func plat_reset_handler
+       /* Only on Cortex-A72 */
+       jump_if_cpu_midr CORTEX_A72_MIDR, a72
+       ret
+
+       /* Cortex-A72 specific settings */
+a72:
+       mrs x0, CORTEX_A72_L2CTLR_EL1
+       orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+       msr CORTEX_A72_L2CTLR_EL1, x0
+       isb
+       ret
+endfunc plat_reset_handler
+
        /* ---------------------------------------------
         * int plat_crash_console_init(void)
         * Function to initialize the crash console